A computer's speed is determined in large part by the speed of the processor and the ability to quickly move data between the processor and memory. The transfer of data from memory has increased with the use of multi-channels, or multiple paths, between the processor and memory.
Latency refers to delays in transmitting data between memory and a processor, and is usually measured in clock cycles. The processor is typically faster than the memory, so it must delay (wait) while the proper segment of memory is located and read before the data can be transmitted back to the processor. Data stored in memory is defined in banks. A rank is a plurality of banks in a first direction (column) and a channel is a plurality of banks in a second direction (row). A process for accessing the memory comprises several clock cycles required for row and column identification and a read or write command. SDRAM is synchronized with a system bus with a synchronous interface and therefore waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus.
A memory controller manages the flow of data going to and from the memory. It may be a separate chip or integrated into another chip, for example, a processor. The bandwidth for the data transfer may comprise a row of many thousands of bits. A double data rate (DDR) memory controller drives memory where data is transferred on the rising and falling access of the memory clock. This DDR memory controller allows for twice the data to be transferred without increasing the clock rate or increasing the bus width to the memory. DDR2 doubles the minimum read or write unit to four consecutive words. DDR3 doubles the minimum read or write unit, again, to eight consecutive words. This provides another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. The downside of this increased read or write unit is an increase in latency.
While memory controllers and methods are known of accessing SDRAM, and memory controllers and methods are known of accessing other types of memory, for example, ST-MRAM, none are known to describe a single memory controller accessing and interleaving both SDRAM and ST-MRAM. ST-MRAM utilizes an alternate method for programming a Magnetic Tunnel Junction (MTJ) element that has the potential to further simplify the MRAM cell and reduce write power. Unlike conventional MRAM where programming is performed with the aid of an external field, ST-MRAM programming is accomplished by driving current directly through the MTJ to change the direction of polarization of the free layer.
DDR3 ST-MRAM has longer ACTIVATE and PRECHARGE operation latencies than those of DDR3 DRAM. During the ACTIVATE operation, a page of data is read from the memory array and stored in local data-store latches for subsequent READ and WRITE operations to the local data-store latches. The ACTIVATE operation can be initiated by an ACTIVATE command or any other command that performs the same operation. During the PRECHARGE operation, the data from local data-store latches are written back to the memory array, and as a result, that page is considered closed or not accessible without a new ACITVATE operation. The PRECHARGE operation can be initiated by a PRECHARGE or AUTO-PRECHARGE command or any other command that performs the same operation. In addition to ACTIVATE and PRECHARGE operation latencies, the page size of ST-MRAM is smaller (for example 512 bits) than that of DRAM (up to 16 k bits). Consequently, an open page in ST-MRAM has a fewer number of bits in the local data-store latches in ST-MRAM chip. The number of READ and WRITE operations (operations in response to READ or WRITE commands that read or write a smaller group of data bits, for example 128 bits, from or to the local data-store latch) to read or write the whole page following an ACITVATE operation to ST-MRAM is smaller than that of the DRAM due to page size difference. When a system uses both DDR3 ST-MRAM and DRAM (due to high density of memory or non-volatility from ST-MRAM memory portion requirements), two or more memory controllers would be needed to manage different latencies and page size in ST-MRAM and DRAM. The DDR3 ST-MRAM would also need dedicated channels (more address, data, control pins and routing) associated with its own memory controller in addition to existing DDR3 DRAM channels.
Accordingly, it is desirable to provide a memory controller and method for interleaving at the rank or channel levels, and reducing latency thereof, a memory consisting of SDRAM and ST-MRAM. Furthermore, other desirable features and characteristics of the exemplary embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.